1. Field of the Invention
The present invention relates to a method of producing a semiconductor memory device, more particularly, to a method of producing a dynamic random access memory (hereafter, called a DRAM) having a fin structure type (lamination type) capacitor formed above a substrate. Furthermore, the present invention relates to a DRAM device, more particularly, to a DRAM device comprising a memory cell portion including a plurality of memory cells and a peripheral circuit. Note, the memory cell includes a transfer gate transistor and a fin structure type capacitor formed above the transfer gate transistor, and the peripheral circuit includes a transistor having a contact hole passing through an insulation layer and reaching to a drain or a source region of the transistor.
2. Description of the Related Art
Recently, a DRAM device having a fin structure type capacitor formed above a substrate has been developed. The fin structure type capacitor is suitable for a mass storage DRAM, for example, 4M bits, 16M bits and the like, as a part of the fin structure type capacitor can be formed on a transfer gate transistor. Therefore, recently, various DRAMs having such a fin structure type capacitor have been studied and proposed.
In such a DRAM, it is required that a parasitic capacitance of a bit line be lowered to decrease power consumption and stabilize operation. Therefore, it is preferable that the thickness of an insulation layer above the bit line, which is provided in the memory cell portion, is thickly formed. Neverthless, when the insulation layer is thickly formed, an aspect ratio of the contact hole formed in the peripheral circuit becomes large. Therefore, coverage of an aluminium wiring layer becomes worse, and the aluminium wiring layer may be snapped.
On the other hand, in order to decrease the aspect ratio of the contact hole formed in the peripheral circuit, a concept of decreasing the thickness of the insulation layer in the peripheral circuit without decreasing the thickness of the insulation layer in the memory cell portion is proposed in Unexamined Japanese Patent Publication (Kokai) No. 02-58866 as a related art. Namely, in JPP '866, it is disclosed that a depth of the contact hole formed in the peripheral circuit is reduced by etching some of the insulation layers and decreasing the thickness of the insulation layers in the peripheral circuit. In a DRAM device in JPP '866, a capacitor is formed above a substrate, but the capacitor is not constituted as a fin structure type capacitor and a silicon nitride (Si.sub.3 N.sub.4) film layer is not provided in the memory cell portion. Therefore, a problem of a shape of the contact hole in the peripheral circuit is not considered. Conversely, in the DRAM device having the fin structure type capacitor, the Si.sub.3 N.sub.4 film layer is necessary for forming the fin structure type capacitor above the transfer gate transistor in the memory cell portion, and the shape of the contact hole in the peripheral circuit is an important problem in terms of reliability of the aluminium wiring. These problems will be described after in detail.